Dielectric noise
Dielectric noise is the thermal noise that comes from the energy an insulator loses when its electric field alternates. In a nanopore measurement the insulators are the membrane, the chip it is mounted on and the supports around the chip, and each acts as a capacitor with some loss in parallel. The loss behaves as a conductance that grows in proportion to frequency, and a conductance at a temperature carries a noise current, so the noise grows with frequency too. It is the main source of nanopore noise in the band from about 2 to 10 kHz, and it is why chips built to be fast are built on glass.[1]
Origin
A capacitor with no loss makes no noise, however much capacitance it has. Callen and Welton showed in 1951 that any system able to dissipate energy has a fluctuation of the matching size, and Nyquist's formula for a resistor is the special case.[2] A real dielectric dissipates through the rotation of dipoles and the migration of charge carriers, and the measure of the loss is the dissipation factor D (the loss tangent, tan δ), the energy lost per cycle as a fraction of the energy stored.[1]
A capacitance C with dissipation factor D has an admittance whose real part is 2πfCD. Each real conductance contributes 4kBT times itself to the spectral density of the current, so
Integrated from zero to a bandwidth B, the power is 4πkBTDC B2, and the rms current is
Noise from the loss is proportional to the bandwidth, where thermal noise from a resistance goes as its square root and noise from the amplifier's input capacitance goes as the bandwidth to the power 3/2. Tabard-Cossa and colleagues used the formula in 2007, in a paper that also showed how to lower the noise.[3]
Size of the effect
The chip dominates. By the parallel-plate estimate, a membrane window 50 µm square of silicon nitride 20 nm thick, taking a relative permittivity of 7, has a capacitance of 7.7 pF. Around it the silicon chip, with its insulating layers over a conducting substrate, measured 368 pF and a loss constant of 0.27 in the study of silicon nitride pores by Smeets and colleagues.[4] The formula gives 22.7 pA rms at 10 kHz for that chip, and 2.3 pA at 1 kHz.
| Chip capacitance | D = 0.0001 | D = 0.01 | D = 0.27 |
|---|---|---|---|
| 1 pF | 0.02 | 0.23 | 1.2 |
| 10 pF | 0.07 | 0.72 | 3.8 |
| 100 pF | 0.23 | 2.3 | 11.9 |
| 368 pF | 0.44 | 4.4 | 22.7 |
Teflon, the usual support for a lipid bilayer, has a dissipation factor of 0.8 to 2 × 10−4 and a relative permittivity of about 1.9, which is the left column. There the noise is set by the thin bilayer, whose capacitance is large, and not by the support, so it falls when the hole in the Teflon is made smaller.[1] Doubling the capacitance or the loss raises the noise by 41%, and doubling the bandwidth doubles it.
Design
Capacitance is the lever, because the dissipation factor of the material is fixed. Tabard-Cossa and colleagues coated the chip around the pore with PDMS, a thick dielectric that lowers the capacitance of the membrane region in series. Glass substrates did more. In 2015 a group made silicon nitride membranes on glass chips with a capacitance below 1 pF and used them for DNA recordings at high bandwidth, where standard silicon chips exceed 300 pF.[5][1] Setting the amplifier beside the pore on a CMOS chip brought the total input capacitance to about 4 pF.[1] A model of the noise of glass and PET supports with single pores matched measurements within 12% from 1 to 40 kHz, with no voltage applied.[6]
Above about 10 kHz the amplifier takes over, as its voltage noise acting on the same capacitance rises faster than the dielectric term (see Nanopore noise).
At Molecular Reality
The open design of the MR1 Nanopore Reader describes its interposer, 0.8 mm thick, as fabricated on "ultra-low-loss PTFE / Rogers RO4350B". The bill of materials gives a relative permittivity of 2.1 for it, and the interposer specification a loss tangent of 0.0002.[7] Those numbers fit PTFE. Rogers publishes a relative permittivity of 3.48 and a dissipation factor of 0.0037 for RO4350B, both at 10 GHz.[8] Fluid channels and electrodes run on the interposer, and the wafer it clamps is silicon, 4 mm square.
The design documents give the capacitance of the membrane and flow cell as 50 to 150 pF. At the loss constant that Smeets measured for a silicon chip, that capacitance gives 8.4 to 14.5 pA rms at 10 kHz from the dielectric term alone. The documented noise floor of less than 1.2 pA rms at 10 kHz would need a loss factor below about 0.006 at 50 pF, before any other source is counted.[a][7]
See also
Notes
- ^ The limit is D = (1.2 pA / 10 kHz)2 / (4πkBT × 50 pF) at 300 K. The design documents quoted here give no loss factor for the chip.
References
- ^ a b c d e Fragasso, A.; Schmid, S.; Dekker, C. (2020). "Comparing current noise in biological and solid-state nanopores". ACS Nano 14 (2): 1338-1349. doi:10.1021/acsnano.9b09353. PMID 32049492.
- ^ Callen, H. B.; Welton, T. A. (1951). "Irreversibility and generalized noise". Physical Review 83 (1): 34-40. doi:10.1103/PhysRev.83.34.
- ^ Tabard-Cossa, V.; Trivedi, D.; Wiggin, M.; Jetha, N. N.; Marziali, A. (2007). "Noise analysis and reduction in solid-state nanopores". Nanotechnology 18 (30): 305505. doi:10.1088/0957-4484/18/30/305505.
- ^ Smeets, R. M. M.; Keyser, U. F.; Dekker, N. H.; Dekker, C. (2008). "Noise in solid-state nanopores". Proceedings of the National Academy of Sciences 105 (2): 417-421. doi:10.1073/pnas.0705349105.
- ^ Balan, A.; Chien, C.-C.; Engelke, R.; Drndić, M. (2015). "Suspended solid-state membranes on glass chips with sub 1-pF capacitance for biomolecule sensing applications". Scientific Reports 5: 17775. doi:10.1038/srep17775.
- ^ Uram, J. D.; Ke, K.; Mayer, M. (2008). "Noise and bandwidth of current recordings from submicrometer pores and nanopores". ACS Nano 2 (5): 857-872. doi:10.1021/nn700322m.
- ^ a b "MR1 Nanopore Reader". GitHub. October 16, 2026.
- ^ "RO4350B laminates". Rogers Corporation. Retrieved October 25, 2026.
